A leadless leadframe package (LLP) is a relatively new integrated circuit package design that contemplates the use of a conductive (typically copper) leadframe type substrate structure in the formation of a chip scale package (CSP). As illustrated in FIGS. 1A–1C, in typical leadless leadframe packages, a copper leadless leadframe panel 100 is patterned (typically by stamping or etching) to define a plurality of device areas 102, which form semiconductor device area arrays 101. One of semiconductor device area arrays 101 is designated with a dashed line in FIGS. 1A and 1B. A device area 102 is designated with a smaller dashed line in FIG. 1B and shown in an enlarged and isolated view in FIG. 1C. Each device area 102 contains the following chip substrate features: a die attach pad 104, a plurality of contacts 106 disposed adjacent to their associated die attach pad 104, and very fine tie bars 108 used to support die attach pads 104 and contacts 106.
During assembly, dice are attached to respective die attach pads 104 and conventional wire bonding is used to electrically couple bond pads on each die to associated contacts 106 on leadframe panel 100. After the wire bonding, a plastic cap is molded over the top surface of each device area array 101. The dice are then singulated into leadless leadframe packaged devices and tested. The conventional sawing techniques used to singulate the packaged leadframe utilizes a saw blade that cuts along and obliterates each of the tie bars. Therefore, after singulation, the only materials holding contacts 106 and die attach pads 104 in place is the molding material. The resulting packaged device can then be surface mounted on a printed circuit board or other substrate using conventional techniques.
Although leadless leadframe packaging has proven to be a cost effective packaging arrangement, there are continuing efforts to further reduce the costs associated with packaging. One persistent issue in packaging generally is the need and desire to provide a leadless leadframe panel that allows for consistent and efficient wire-bonding throughout the leadless leadframe panel. Currently, different pressures are applied to a wire-bonding mechanism to wire-bond semiconductor dice to contacts 106 depending upon the location of specific contacts 106 within each device area array 101. Specifically, larger amounts of pressure are required to attach wires to contacts 106 that are located in the interior regions of device area arrays 101 relative to contacts 106 located on the peripheral edges of arrays 101. This is because contacts 106 along peripheral edges of arrays 101 are firmly supported by relatively rigid lengthwise rails 112 and widthwise rails 114. The firm support provided by rails 112 and 114 allows these peripheral contacts to remain relatively stiff during wire-bonding processes and therefore allows for lesser wire-bonding forces to effectively attach wires to the contacts. On the other hand, the interior contacts tend to flex during wire-bonding processes because they are not firmly supported by either lengthwise rails 112 or widthwise rails 114. Therefore, greater pressure is required for effective wire bonding. Since the wire-bonding forces vary, the wire-bonding process is not optimized and will generally result in lifted or chopped welds causing semiconductor package failures; hence, production yields are reduced.
Another issue is the need for a leadless leadframe panel that is securely attached to the molding material that is eventually molded over each of device area arrays 101. Specifically, secure attachment about the peripheral edges of device area arrays 101 would tend to reduce the amount of chipping of the molding material around the corners of each device area array 101 that occurs during singulation. Chipping typically occurs because the rotating saw blade used to singulate device area arrays 101 into individual semiconductor device packages causes vibration of the peripheral edges of the molding material and panel 100. Therefore the saw blade tends to erratically cut through and chip the molding material panel at the corners of device area arrays 101 since the corners of the molding material are not firmly attached to panel 100. In addition, chipping typically occurs when the rotating saw blade cuts perpendicularly into lengthwise rails 112 and widthwise rails 114 because vibrations from the abrupt encounter by the saw blade with the rigid rails are transferred to the corners of the semiconductor device packages positioned in the immediate vicinity. Consequently, corner chipping occurs and may lead to functional failures of the semiconductor device package. Again, a reduction of production yields would result.
There is also the need to provide a leadless leadframe panel that reduces the amount of uneven wear on the saw blades used for singulation. Specifically, a saw blade wears unevenly when cutting along the periphery of device area arrays 101 in order to singulate the semiconductor device packages from therein. As can be seen, lengthwise rails 112 and widthwise rails 114 substantially support the spaced apart contacts 106 that are positioned along the periphery of device area arrays 101. However, as a saw blade cuts along the periphery of device area arrays 101, the blade encounters portions where there is a solid rail on one side and a gap of open area that may be filled by molding material on the other side. In addition, the blade also encounters portions where there is a solid rail on one side and a contact 106 on the other side. Alternatively, the blade may encounter portions where there is molding material on both sides. Therefore, the two sides of a saw blade wear unevenly when cutting along the periphery of device area arrays 101. This in turn may cause damage to the semiconductor device package being cut. Furthermore, subsequent cuts with an uneven blade may cause damage to subsequent singulated semiconductor device packages.
In view of the foregoing, simple, low cost methods and apparatuses for improving the production yield of leadless leadframe packages would be desirable.